Chips including semiconductor integrated circuits undergo a variety of tests to determine whether the semiconductor devices are operating properly. There are various stages of testing to screen defective and/or underperforming chips to avoid the cost of passing along a bad chip onto the next level of assembly. For example, the various stages of testing during each level of assembly include wafer level testing, package level testing, board level testing and system level testing. The quicker a bad chip is discovered, less wasted cost is incurred since it is removed from the assembly chain. That is, the amount of loss due to a bad chip at wafer level is lower than the amount of loss due to bad part at system level due to waste of material and efforts spent at subsequent stages of building a system and processes. So it is essential to screen the parts at each level.
In particular, scan based tests of the circuits may be performed to test one or more similarly configured chips. Scan based tests of circuits on a chip include “scan shift” and “scan capture” operations. These scan based tests can operate on a scan chain of connected registers (e.g., flip-flops or latches) that are designed for testing by inputting data and analyzing the output data from each of the scan chains.
During production level testing on ATE, automatic test pattern generator (ATPG) test patterns are typically run to screen the bad chips from good chips. ATPG test patterns are mainly run on automatic test equipment (ATE) during production testing at wafer level or/and package level to test chips in parallel.
It is desirable to run system level testing to perform routine maintenance, and perform failure testing. In a practical example, chips may be used in the infotainment system of automobiles. The need to run online system level tests of chips already integrated into the infotainment system at the system level (i.e., after the automobile is ready for consumer purchase) is mandatory in the industry. For instance, it is necessary to perform fault diagnosis and testing during the maintenance of the automobile system. On-line testing and diagnostics may follow industry standards, such as the functional safety standard for automobiles (e.g., ISO 26262) outlining functional safety features at each phase of product development for automobiles. On-line testing and diagnostics may be performed to determine failure in time (FIT) rates, reliability grading, and resiliency grading for mission critical applications. In addition, system level testing may be performed on a field return part, wherein a chip which passes production testing incurs a failure when implemented into a system. As such, it is necessary to support online testing and diagnostics in automobile applications for these specialized chips.
The biggest problem is that ATPG test patterns are difficult to implement at the system level, such as when performing online logic testing. System level testing heretofore included running scan debug tests, wherein all test scan chains are stitched into one single, long chain. The combined scan chain is driven from a test (e.g., TCK) clock. However, this scan debug test seems to be very slow because of the large number of flops in the chains that need to be loaded and unloaded. Also, ATPG test patterns cannot be directly applied in scan debug mode. Further, the additional infrastructure needed on a chip to support a scan debug mode is costly, and cannot be accommodated within the tight confines of the automobile cabin. As such, a scan debug mode is not feasible for performing system level testing.
Also, customers would like to run self-test patterns, such as logic built in self test (BIST) during power-on at the system level to made sure that the chip is still fully functional, before entering into mission mode. However, logic BIST test approaches are different depending on the chip and the electronic design automation (EDA) tool support. In most cases, the logic BIST does not provide higher test coverage because of the random patterns. As such, it is not suitable or economical to implement logic BIST for the purpose of running online system level testing.